Tan Bui-Thanh, The University of Texas at Austin, United States

Tan Bui-Thanh
The University of Texas at Austin, United States
Tan Bui is a Professor and the Endowed William J. Murray, Jr. Fellow in Engineering No. 4 at The University of Texas at Austin (Oden Institute for Computational Engineering and Sciences and the Department of Aerospace Engineering and Engineering Mechanics). He is also the Director of the Center for Scientific Machine Learning. He earned his Ph.D. in Computational Fluid Dynamics from the Department of Aeronautics and Astronautics, Massachusetts Institute of Technology, in 2007, where he developed model-constrained model-reduction methods for large-scale aerodynamic systems. For over 26 years, his career has focused on computational science, engineering, and mathematics, advancing the mathematical, algorithmic, and computational foundations needed for reliable prediction, inversion, and uncertainty quantification in complex multiscale, multiphysics systems governed by partial differential equations. Professor Bui has held several leadership roles in the scientific computing community, including elected Vice President of the SIAM Texas–Louisiana Section and elected Secretary of the SIAM Activity Group on Computational Science and Engineering (SIAG/CSE). His honors include an NSF CAREER Award (jointly funded by the Office of Advanced Cyberinfrastructure and the Division of Mathematical Sciences), the Oden Institute Distinguished Research Award, two Moncrief Faculty Challenging Awards, and recognition as a Gordon Bell Prize finalist.

Abstract:
We develop a probabilistic framework for planning optimal contact points with a moving agent whose trajectory is uncertain but approximately optimal. The target's motion is modeled as a stochastic process consistent with a Hamilton–Jacobi principle of optimality, where uncertainty arises both from sensing noise and from ambiguity in model parameters such as target location or turning radius. This uncertainty induces a mixture model over possible trajectory distributions, leading to a stochastic optimization problem that seeks a small set of space–time contact points maximizing the probability of successful interception.
Furthermore, we seek to intercept the agent's trajectory before it arrives at its target. We formulate this objective as a min–max optimization over parameter hypotheses and derive a structural characterization of the optimal solution. In particular, we show that the support of the optimal sampling distribution lies within the union of Pareto–optimal intercept configurations, each corresponding to a convex combination of parameter-conditioned success probabilities. This result provides a principled foundation for planning under uncertainty in applications such as autonomous rendezvous, probabilistic interception, and multi-agent coordination, where near-optimal but uncertain motion models are available.

Cong-Kha Pham, The University of Electro-Communications, Japan

Cong-Kha Pham
The University of Electro-Communications, Japan
Cong-Kha Pham received B.S., M.S., and Ph.D. degrees in Electronics Engineering from Sophia University, Tokyo, Japan. He is currently a professor with the Department of Information and Network Engineering, University of Electro-Communications (UEC), Tokyo, Japan. His research interests include hardware system design and implementation by FPGAs and integrated circuits. Recent projects include research on energy harvest power supply and low-power data-centric sensor network systems utilizing them, the development of long-distance transmission and miniaturization equipment for sensor networks by low-power wireless, the super low-voltage device project, research on memory-based information detection systems, the hardware implementation of hardware systems by FPGAs and integrated circuits, etc. Professor Pham teaches many undergraduate and postgraduate students and has received numerous awards for dissertations. The University of Electro-Communications Integrated Circuit Design Laboratory (Pham Lab) educates on the design, implementation, and evaluation of hardware systems and VLSI, aims to design “system-on-chip” by integrating various information processing hardware, and develops a high-performance computational circuit realized with a small number of elements.

Abstract:
The breakdown of Moore's Law has shifted deep learning acceleration from compute-bound to memory-bound optimization, compelling comprehensive co-design across multiple abstraction layers. This analysis examines co-design methodologies spanning algorithm-architecture, architecture-physics, and integration-system domains for AI hardware, where conventional silicon approaches face fundamental limitations.
CNN accelerators exploit spatial locality while GNN accelerators address irregular access patterns through work allocation strategies and load-balancing techniques; transformer-based LLMs accelerators concurrently tackle attention complexity and memory wall constraints via key-value cache optimizations and hierarchical data compression. Edge inference systems exemplify hardware-constrained adaptation through quantization and structural pruning techniques, reducing model complexity to match fixed physical resources.
Architecture and physics co-design method such as processing-in-memory architectures, non-volatile memory interfaces, and neuromorphic computing, directly challenge von Neumann bottlenecks by integrating computation with storage at the circuit level. Chiplet ecosystems, 3D stacking, and advanced interconnect architectures enable system scaling beyond single-die limitations, with thermal management and power delivery emerging as critical factors in post-Moore hardware deployment.
Sustainable AI acceleration requires holistic optimization across algorithmic design, architectural innovation, device physics, and system integration, establishing research directions in memory-centric co-design, cross-layer optimization, and physical layer innovation for next-generation AI hardware.

Nguyen H. Tran, The University of Sydney, Australia

Nguyen H. Tran
The University of Sydney, Australia
Nguyen H. Tran (S'10-M'11-SM'18) received BS and PhD degrees (with the best PhD thesis award in 2011) from HCMC University of Technology and Kyung Hee University, in electrical and computer engineering, in 2005 and 2011, respectively. Dr Tran is an Associate Professor at the School of Computer Science, The University of Sydney. His research group has special interests in Distributed compUting, optimizAtion, and machine Learning (DUAL group). He received funding from the Korea NRF for Basic Science and Research (2016-2023), the ARC Discovery Project (2020-2023), and the SOAR award (2022-2023). He serves as an Editor for several journals, including IEEE Transactions on Green Communications and Networking (2016-2020), IEEE Journal of Selected Areas in Communications (2020), and IEEE Transactions on Machine Learning for Communications and Networking (2022-2025), in the area of distributed machine learning.

Abstract:
Large language model inference, despite its reputation as a compute problem, is fundamentally bottlenecked by memory bandwidth, and this single fact reshapes how distributed edge intelligence should be designed. In this keynote I argue that once inference moves off a single device and onto a swarm of heterogeneous edge clients sharing a remote verifier, the central question stops being “how do we run the model faster” and becomes “how do we fairly allocate a contended resource under uncertainty”: a problem networking solved twenty years ago. I make this case concrete through GoodSPEED (INFOCOM 2026), our recent work that reframes distributed speculative decoding as a proportional-fairness scheduling problem. I then situate GoodSPEED within a broader research program I call Edge Distributed Generalised Intelligence (Edge DGI), which asks (i) how heterogeneous edge devices can collectively learn, reason, and generalise, and (ii) what fundamental capacity bound limits what a distributed swarm can collectively know. The talk closes with open problems spanning privacy-preserving speculation, adversarial drafters, cross-modal extensions, and the theoretical work needed to tighten the Edge DGI capacity bound into a usable design principle.